PhaseSCA: Exploiting Phase-Modulated Emanations in Side Channels

Authors

  • Pierre Ayoub EURECOM, Sophia Antipolis, France
  • Aurélien Hernandez EURECOM, Sophia Antipolis, France
  • Romain Cayre EURECOM, Sophia Antipolis, France
  • Aurélien Francillon EURECOM, Sophia Antipolis, France
  • Clémentine Maurice Univ. Lille, CNRS, Inria

DOI:

https://doi.org/10.46586/tches.v2025.i1.392-419

Keywords:

Side-channel attacks, Power/Electromagnetic analysis, Unintended modulation, Phase modulation, Angle modulation, Clock jitter

Abstract

In recent years, the limits of electromagnetic side-channel attacks have been significantly expanded. However, while there is a growing literature on increasing attack distance or performance, the discovery of new phenomenons about compromising electromagnetic emanations remains limited.
In this work, we identify a novel form of modulation produced by unintentional electromagnetic emanations: phase-modulated emanations. This observation allows us to extract a side-channel leakage that can be exploited to reveal secret cryptographic material. We introduce a technique allowing us to exploit this side-channel in order to perform a full AES key recovery, using cheap and common hardware equipment like a software-defined radio (SDR). Moreover, we demonstrate that the exploitation of this new phase leakage can be combined with traditional amplitude leakage to significantly increase attack performance. While investigating the underlying phenomenon causing this unintentional modulation, we identified several prior works that have approached similar exploitation – without being aware of each other. Creating a bridge between older and recent work, we unveil the relationship between digital jitter and signal phase shift in the context of side-channel attacks and fill the gap between prior works from various research fields.

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Published

2024-12-09

Issue

Section

Articles

How to Cite

PhaseSCA: Exploiting Phase-Modulated Emanations in Side Channels. (2024). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 392-419. https://doi.org/10.46586/tches.v2025.i1.392-419